The invention relates to field programmable integrated circuit logic devices or arrays (PLAs), such as those devices known as field programmable gate arrays (FPGAs) or erasable programmable logic devices (EPLDs).
Programmable logic devices such as PLAs, PALs, ASICs, FPGAs and EPLDs are well known in the field. Such devices are described in such prior publications as Birkner, U.S. Pat. No. 4,124,899; Freeman, U.S. Pat. No. 4,870,302; Carter, U.S. Pat. No. 4,706,216; Elgamal et al., U.S. Pat. No. 4,758,745; and Kaplinsky, U.S. Pat. 4,847,612. All these patents are incorporated herein by reference. These devices all have hardware which can be programmably connected together to perform a logic function selected by a user. Once these devices have been programmed by the user, certain external pins serve as input pins, others pins serve as output pins and in some cases some serve as input/output pins. The device provides signals on the output pins in response to signals and combinations of signals placed on input pins as determined by the function which has been programmed into the device by the user.
Users employ these programmable devices to solve a wide variety of problems, and manufacturers have responded by offering a wide variety of device sizes and speeds as well as device designs. Some devices are optimized for speed, some for flexibility, some for complexity, and some for low cost. Typically higher speed, higher flexibility, and larger size are each associated with higher cost. With existing devices, high speed is typically provided and must be paid for whether the user needs it or not. Some users want a large number of signal pins but can tolerate low speed output buffers. No device with these characteristics has been available.
In accordance with the present invention, an input/output buffer is provided, particularly useful with a microprocessor controlled device which appears to a user to be a programmable logic device. Signals are taken from and placed on external pins in the same manner as would be done with a prior art programmable logic device. The microprocessor is programmable to read input signals from input pins, perform calculations related to the desired logic, and place signals on output pins. Thus the function of the microprocessor controlled device as it appears from observing signals on external pins is the same as that of a prior art FPGA or other logic device.
In accordance with a second aspect of the present invention, an FPGA input/output buffer including a tristate enable register is provided. This register controls the conductivity of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the register. In some embodiments, a plurality of pads attached to external pins are driven by tristate buffers, some of which may have registers controlling both the conductivity state of the tristate buffers and providing data to the tristate buffers, and other pins have registers controlling the conductivity state of the tristate buffers but receive asynchronous signals on the data terminals of the tristate buffers.